Computer Architecture

Draw the Von-Neumann architecture. What is meant by Von- Neumann bottleneck ?

Von-Neumann and his colleagues began the design of a new stored-program  computer in  1946,   known as the IAS computer at the Princeton Institute for Advanced Studies The IAS computer is the prototype of subsequent general purpose computers The general structure of the IAS computer is shown in fig.

  1.   A main memory that stores both data and instructions.
  2.  An arithmetic and I logic unit (ALU) capable of operating on binary data.
  3.  A control unit that interprets the instructions in memory and causes them to be executed.
  4.  Input and output equipment operated by the control unit.

fig02. Von Neumann architecture

The Von Neumann architecture is a standard design of computer system with different entities connected over a bus. 

1) Input/output or I/O Unit 

2) A central processing unit (CPU) 

3) Dedicated registers

4) Buses

I/O Devices

Inputs are the signals or data received into the computer system from the outside world via input devices. The data is stored in internal registers. 

Outputs are the signals or data returned from the computer system to the outside world via output devices. Together these peripheral devices form the I/O unit. 

The Processing unit

The CPU is responsible for carrying out the fetch-decode-execute cycle. The CPU fetches instructions and data from the RAM or cache, decodes then executes.

It is separated into the ALU (Arithmetic logic unit) and a Control Unit


This calculates the arithmetic logic of instructions from programs (carries out calculations on the data) needed by programs. It can carry out simple calculations like adding/subtracting/multiplying/dividing and make logic operations like `greater than’ or `less than’ or `equal to’. It also acts as a conduit for input and output to and from the processor.

Control Unit

This controls the flow of data through the processor. It manages the execution of machine code by sending control signals to the rest of the computer. Control signals are sent over the control bus to connected devices like hard drives and graphics cards. The control unit synchronizes instructions to the internal clock speed. Some instructions can take less than one clock cycle to complete but the CPU will only start on the next instruction once the clock cycle is over. The control unit command for instructions and data to be fetched by assigning control signals to the memory registers. Once the instruction is decoded it sends more signals to the hardware to execute it  (i.e. it tells the computers’ memory, ALU and I/O devices how to respond to an instruction). 

Memory unit

The memory unit is responsible for fetching data and instructions from the main memory and pulling them into registers needed for the data to be processed. An instruction can only run on data within a register so the memory unit is responsible for fetching from and saving to memory. Therefore the memory unit makes use of what is known as the fetch-decode-execute cycle. 

Processor speed

This is measured by the number of clock cycles a processor can perform per second and is measured in hertz (Hz). 

Clock cycle = One increment of the CPU clock (fetch-decode-execute a single instruction). 

Bus types

The bus is a set of parallel wires connecting two or more components of a computer. It typically consists of 8, 16, 32 or 64 lines. They connect all the components (I/O devices) to the CPU and RAM and allow the transfer of data between the components.

•        Address bus: is used to identify locations in other components by transferring memory addresses to either the memory or the I/O controller. Unidirectional flow. The address may be for a location of an instruction or piece of data to be fetched or stored. 

•        Control bus – is used to send signals that coordinate the flow of data and manage the activities of the peripheral devices. It transmits command, timing and specific status information between components. 

•        Data bus – transfers data and instructions between peripherals, memory and the CPU. 

These 3 buses are commonly collectively called the system bus. Each bus is a shared transmission medium, so only one device can transmit along the bus at any given time. 

(The von Neumann architecture has only one data bus so data transfers and instruction fetches are scheduled: They cannot run simultaneously).

The main idea the Von Neumann architecture introduced was that not only the data but also the program processing the data should also be stored in the memory. This made it easy to reprogram the computer.

The control bus is bidirectional so signals can be transferred in both directions. The data and address buses are shared by all components in the system. Control lines must, therefore, be provided to ensure access and use of the data and address buses by different components does not conflict. 

Von- Neumann bottleneck

Von-Neumann Bottleneck – A computer’s performance is also strongly affected by other factors besides its instruction set, especially the time required to move instructions  and data between the CPU and main memory M and to a lesser extent, the time required to move information between M and I/O device. It typically takes the CPU about five times longer to obtain a word from M than from one of its internal registers. This difference in speed has existed since the first electronic computers, despite strenuous efforts by circus as designers to develop memory devices and processor-memory interface circuits  that are fast enough to keep up with the fastest microprocessors.

Indeed the  CPU-M-Speed disparity has become such a feature of standard (Von-Neumann)

computers that are sometimes referred to as the Von-Neumann bottleneck. RISC computers usually limit access to main memory to a few load and store instructions, other instructions, including all data processing and program- control instructions, must have their operands in CPU registers. This so-called load-store architecture is intended to reduce the impact of the Von-Neumann bottleneck by reducing the total number of the memory accesses made by the CPU. Caches directly address the Von-Neumann bottleneck by providing the CPU with fast, single-cycle access to its external memory.

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